1. Field of the Invention
The present invention relates to a transmitter circuit and a receiver circuit for communication that are synchronized with a clock and execute data signal processing.
2. Description of the Prior Art
Recently, to increase data communications traffic, the enhancement of the data rate of a communication system is demanded and high-speed performance is essential for an element circuit of the system. Particularly, concerning a circuit for optical communication, to utilize the very high speed transmission characteristic of an optical fiber to the maximum, the enhancement of the operating speed is strongly demanded.
Factors which limit a data rate will be described below. To transmit at precise timing, a circuit for communication is operated in synchronization with an external reference clock. In transmitting, a data waveform is shaped using a clock signal and data is transmitted, and in receiving, data is decided using the clock signal extracted from a received data waveform. As a clock signal determines the transmission of data and the timing of receiving, the maximum frequency of the clock signal determines a maximum operation frequency required in a communication circuit as it is.
That is, as the clock signal has the highest frequency component in the circuit for communication, the upper limit of the operation frequency of its clock signal processing circuit is required to exceed at least the frequency of the clock signal. In a high frequency, the upper limit of the operation frequency of the clock signal processing circuit is determined under the effect of the characteristics of devices forming the circuit and a wire parasitic element. In case a clock signal equal to or exceeding the operating frequency is input to the clock signal processing circuit, the amplitude of the clock signal decreases and therefore, an error occurs in the operation of a circuit of a synchronous type such as a flip-flop. Therefore, the maximum operation frequency of the clock signal processing circuit is an important element that determines the operation frequency of the circuit for communication.
In such a circuit for optical communication, a system in which a transmitter circuit and a receiver circuit respectively formed using a circuit of a synchronous type are connected via an optical fiber as shown in FIG. 2 is known. (For example, see FIG. 1 in a non-patent document 1. It is hereinafter called a conventional type example 1.)
As shown in FIG. 2, parallel data signals and a clock signal are input to the transmitter circuit TRM. A multiplexer (MUX) 30 is a circuit for time-division multiplexing the parallel data signals to a serial data signal. “m” pieces of parallel data signals can be multiplexed to a serial data signal of a data rate of f1 b/s at a data rate f1/m b/s. In this case, “m” is the power of 2 and FIG. 2 shows a case of “m=4”. The multiplexed data signal is converted to an optical signal via an electrical/optical converter composed of a laser diode 40, a modulator 41 and a driver 42.
The optical signal input to the receiver circuit RCV via an optical fiber 33 is converted and amplified to an electrical signal by a photo diode 31, a preamplifier 32 and a main amplifier 35. This signal is demultiplexed, one is input to a decision circuit 36 and the other is input to a clock extracting circuit 2a. The clock extracting circuit 2a is a circuit for recovering the clock signal based upon the data signal. The decision circuit 36 decides and outputs a code of data at precise timing using the recovered clock signal and inputs it to a demultiplexer (DEMUX) circuit 34. The demultiplexer circuit 34 demultiplexes and outputs the serial data signal of the data rate of f1 b/s to the “m” pieces of parallel data signals at the data rate of f1/m b/s using a clock signal acquired by dividing the recovered clock signal into a frequency f1/2 Hz in a frequency divider 20. According to this configuration, “m” pieces of data signals of the data rate of f1/m b/s which can be easily processed in an electrical circuit can be transmitted simultaneously and in parallel on one optical fiber. In FIG. 2, an external clock having a frequency of 5 GHz is input to the transmitter having a data rate of 10 Gb/s.
In case a circuit for communication is actually applied to an optical transmission system, it is strongly demanded to reduce the jitter of an output waveform and to retime so as to possibly reduce a communication error. Therefore, a master-slave-D flip-flop MS for retiming is arranged next to the output of the multiplexer MUX as shown in FIG. 3 (For example, see FIG. 1 in a non-patent document 2. It is herein after called a conventional type example 2), and a clock signal having a frequency of f1 Hz is input to data of the data rate of f1 b/s so as to shape its waveform.
A clock signal having the frequency of f1 Hz is also input to the receiver circuit so as to drive the decision circuit 36 and a waveform is precisely reshaped. In FIG. 3, a reference number M denotes a master of the master-slave D flip-flop and S denotes a slave of the master-slave D flip-flop. A reference number 20a denotes a frequency divider, 23 denotes a data output buffer circuit, 24 denotes a phase shifter circuit that enables the phasing of a clock signal so that the clock signal is input at a suitable time slot, 25 denotes a clock buffer circuit, and T1 and T2 denote a control signal input terminal for controlling a phase.
Operation using a clock having the frequency of f1 Hz at the data rate of f1 b/s is called full rate operation. In not only the configuration of the transmitter circuit shown in FIG. 2 but the configuration of a circuit shown in FIG. 4 (For example, see FIG. 16 in the non-patent document 1. It is hereinafter called a conventional type example 3), a clock signal having a frequency of 20 GHz is also input to data of a data rate of 40 Gb/s in a receiver circuit RCV. As described above, the operation of the transmitter circuit and the receiver circuit using a clock signal having the frequency of f1/2 Hz at the data rate of f1 b/s is called half rate operation.
[Non-Patent Document 1]
pp. 347 to 383 of “Si and SiGe BIPOLAR ICs for 10 TO 40 Gb/s OPTICAL-FIBER TDM LINKS” written by H.-M. REIN and published in 1998 by World Scientific Publishing Company in Vol. 9, No. 2 of International Journal of High Speed Electronics and Systems
[Non-Patent Document 2]
pp. 129 to 132 of Vol. 30 of “A 12-Gb/s Si Bipolar 4:1-Multiplexer IC for SDH Systems” written by Z. H. Lao, et al. and published in 1995 in Vol. 30, No. 2 of IEEE Journal of Solid-state Circuits